The present invention relates to a gate driver for power semiconductor devices.
Many low voltage electronic circuits, e.g., MOSFET devices, are used to drive high voltage switching transistors, e.g., power MOSFETs, insulated gate bipolar transistor devices (IGBTs), gate controlled thyristors, and the like. A power semiconductor switch or device is switched from a nonconducting state to a conducting state by raising the gate-source voltage from below to above a threshold voltage.
One or more low voltage transistors, coupled to an output node of the gate driver, apply appropriate voltages to the gate or control terminal of the power device to turn on or turn off the power device. When the power device is an N-channel metal oxide semiconductor field effect transistor (NMOSFET), the device is turned on by applying a high voltage to the gate of the power switch and turned off by applying a low voltage to the gate. In contrast, if the power device is a P-channel metal oxide semiconductor field effect transistor (PMOSFET), the device is turned on by applying a low voltage to the gate of the power switch and turned off by applying a high voltage to the gate.
Circuitry of the gate driver may be configured a number of different ways. In one common configuration, the gate driver includes two transistors, i.e., upper and lower transistors, connected in series in a half bridge configuration. The upper transistor is a P-type transistor, such as a PMOSFET or PNP bipolar transistor. The lower transistor is an N-type transistor, such an NMOSFET or NPN bipolar transistor. An output node of the gate driver is coupled to a node between the two transistors to output and apply a high or low potential to the gate of the power switch according to the conductive states of the two transistors in series.
In one embodiment, a power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device. The gate driver is configured to output a first conductive state, a second conductive state, and a third conductive state. A pull-down resistor has a first end and a second end. The first end of the pull-down resistor is coupled to the output node of the gate driver.
In another embodiment, a gate driver for a power semiconductor device includes an output node to apply a first electrical state, a second electrical state, and a third electrical state to the power semiconductor device. A first input node receives a first input signal or a second input signal. A second input node receives an enable signal or a disable signal. The output node of the gate driver is at the third electrical state if the disable signal is received at the second input node regardless of any signal received at the first input node. The output node of the gate driver is at the first electrical state if the enable signal is received at the second input node and the first input signal is received at the first input node. The output node of the gate driver is at the second electrical state if the enable signal is received at the second input node and the second input signal is received at the first input node.
In yet another embodiment, a gate driver for a power semiconductor device includes an output node to apply a first electrical state, a second electrical state, and a third electrical state to the power semiconductor device. A first input node receives a first input signal or a second input signal. A second input node receives an enable signal or a disable signal. A P-type transistor has a terminal coupled to the output node of the gate driver. An N-type transistor has a terminal coupled to the output node of the gate driver. The disable signal received at the second input node turns off the fist and second transistors.